(a) Fields of the Invention
The present invention relates to semiconductor memory devices, and in particular to nonvolatile semiconductor memory devices such as EEPROMs (electrically erasable programmable read-only memories).
(b) Description of Related Art
In a semiconductor memory device, the state of data, “0” or “1”, stored in a memory cell to be read is determined in the manner in which a predetermined voltage is applied to a gate electrode of the target memory cell to utilize a change in threshold voltage differing depending on the quantity of electrical charges in a charge storage layer thereof. To operate the device in this manner, in the device, a memory cell array is constructed so that in a plurality of memory cells, collective connection is made among respective gate electrodes, respective drain regions, and respective source regions and that the memory cells are arranged in rows and columns on a semiconductor substrate. The gate electrodes of the memory cells continuously extend along the row direction of the memory cell array, and serve as a word line. The drain regions of the memory cells aligned along the column direction of the memory cell array are collectively connected to a bit line, and the source regions thereof aligned along the column direction of the memory cell array are collectively connected to a source line.
In the memory cell array, a protective diode is typically connected to an end of the word line in order to prevent the gate electrode from being electrically charged during a device fabrication process as will be described below.
FIG. 32 shows a cross-sectional structure of a connecting portion between a word line and a protective diode in a conventional memory cell array used in general (see, for example, Japanese Unexamined Patent Publication No. H10-173157).
Referring to FIG. 32, in the upper portion of a p-type semiconductor substrate (or a p-type well) 101, a memory cell array region A and a protective diode region B are formed which are defined by an isolation insulating film 102. In the memory cell array region A, a plurality of gate insulating films are disposed in rows and columns, and each of the gate insulating films is formed by sequentially stacking a first gate oxide film 103, a charge storage layer 104, and a second gate oxide film 105 on the p-type semiconductor substrate 101. On the second gate oxide films 105, a plurality of word lines 108 are formed which extend in the row direction and also serve as gate electrodes.
A source/drain diffusion layer 106 is formed in an area of the upper portion of the p-type semiconductor substrate 101 which is located between the gate insulating films extending in the column direction. An insulating film 107 is formed between the source/drain diffusion layer 106 and the word line 108.
In the protective diode region B adjacent to the memory cell array region A, the n-type diffusion layer 109 is formed in the upper region of the p-type semiconductor substrate 101. The n-type diffusion layer 109 and the p-type semiconductor substrate 101 constitute a protective diode element.
The n-type diffusion layer 109 of the protective diode element and an end of the word line 108 are electrically connected through a first metal interconnect 111 and contacts 110 made of refractory metal.
In various processes for forming the semiconductor memory device, particularly in formation processes using plasma, resulting electrical charging of the word line 108 may raise the potential of the word line 108. In this case, if no current pass is provided to the word line 108, voltage drop at the word line 108 does not occur and thus the word line 108 is kept at a high potential. For example, positive charging of the word line 108 is equivalent to the state in which a positive voltage is applied to the word line 108. As a result, electrons are injected from the source/drain diffusion layer 106 to the charge storage layer 104. On the other hand, negative charging of the word line 108 is equivalent to the state in which a negative voltage is applied to the word line 108. As a result, holes are injected from the source/drain diffusion layer 106 to the charge storage layer 104 or electrons are injected from the word line 108 to the charge storage layer 104.
As described above, in the memory cell, the state of data, “0” or “1”, is determined by sensing a change in threshold voltage caused by storing charges in the charge storage layer 104. Therefore, the threshold value of the memory cell immediately after completion of fabrication is affected by the change in the quantity of charges in the charge storage layer 104 due to electrical charging of the word line 108 during the formation processes, which will cause malfunction in determining data. Furthermore, the state in which the potential of the word line 108 becomes high due to electrical charging gives stress to the gate oxide films 103 and 105, which disadvantageously degrades the film qualities of the gate oxide films 103 and 105 to shorten their lifetime.
In order to deal with this problem, generally, as shown in FIG. 32, the word line 108 is connected through, for example, the first metal interconnect 111 to the protective diode region B. Thereby, the word line 108 is protected from a high voltage applied in formation processes subsequent to the word line formation process.
However, in the conventional method for fabricating a semiconductor memory device, when the approach of connecting the word line 108 to the protective diode region B through an interconnect layer such as the first metal interconnect 111 is taken, the functions of the protective diode region B cannot be utilized by the time the interconnect layer is formed, specifically, until a conductive film for forming an initial interconnect layer is deposited.
In particular, in the formation process of the contact 110 shown in FIG. 32, a thermal treatment at a relatively high temperature (650° C. or higher) can be performed before formation of a refractory metal film made of, for example, tungsten used as the material for the contact 110. Even though charges are stored in the charge storage layer 104 by electrical charging of the word line 108 during the fabrication process, addition of high-temperature thermal treatment allows release of the stored charges. However, such a high-temperature thermal treatment cannot be performed after formation of the refractory metal film for contact formation, so that it is impossible to release charges stored in the charge storage layer 104.
Typically, in a contact formation process, plasma is used in sputtering growth of a metal film including dry etching of a contact hole, and the like. Thus, the approach of connecting the word line and the protective diode region through the interconnect layer causes a problem that charge injection into the charge storage layer due to electrical charging of the word line cannot be prevented during a period of time between the instant when deposition of a conductive layer for word line formation and subsequent formation of the refractory metal film in the contact formation process are both completed and the instant when the interconnect layer is formed, to be more specific, the instant when the conductive film for forming the initial interconnect layer is deposited.